Claude-skill-registry esmt

ESMT (Elite Semiconductor Memory Technology) MPN encoding patterns, suffix decoding, and handler guidance. Use when working with ESMT DRAM and Flash memory components or ESMTHandler.

install
source · Clone the upstream repo
git clone https://github.com/majiayu000/claude-skill-registry
Claude Code · Install into ~/.claude/skills/
T=$(mktemp -d) && git clone --depth=1 https://github.com/majiayu000/claude-skill-registry "$T" && mkdir -p ~/.claude/skills && cp -r "$T/skills/data/esmt" ~/.claude/skills/majiayu000-claude-skill-registry-esmt && rm -rf "$T"
manifest: skills/data/esmt/SKILL.md
source content

ESMT (Elite Semiconductor Memory Technology) Manufacturer Skill

MPN Structure

ESMT MPNs follow this general structure:

[PREFIX][DENSITY][CONFIG][VERSION]-[SPEED][PACKAGE]
   |       |        |       |        |        |
   |       |        |       |        |        +-- Package code (TG, BG, etc.)
   |       |        |       |        +-- Speed grade (6, 5, 2.5, 100, 70)
   |       |        |       +-- Version letter (A, B, etc.)
   |       |        +-- Memory configuration (bus width, banks)
   |       +-- Density in Mbit
   +-- Series prefix (M12L, M14D, F25L, F49L)

Example Decoding

M12L128168A-6TG
|  |   |  ||  ||
|  |   |  ||  |+-- TG = TSOP-II package
|  |   |  ||  +-- 6 = 6ns speed grade
|  |   |  |+-- A = version/revision
|  |   |  +-- 8 = 8 banks
|  |   +-- 16 = 16-bit data bus
|  +-- 128 = 128 Mbit density
+-- M12L = SDRAM series

F25L016A-100PAIG
|  |  ||    | ||
|  |  ||    | |+-- IG = Industrial grade
|  |  ||    | +-- PA = SOP package
|  |  ||    +-- 100 = 100MHz speed
|  |  |+-- A = version
|  |  +-- 016 = 16 Mbit
|  +-- 25L = SPI Flash series
+-- F = Flash prefix

Series Prefixes

PrefixMemory TypeDescription
M12LSDRAMSynchronous DRAM
M14DDDR SDRAMDDR1 SDRAM
F25LSPI FlashSerial SPI NOR Flash
F49LParallel FlashParallel NOR Flash

Density Codes

SDRAM (M12L) and DDR (M14D)

CodeDensityNotes
1616 Mbit
3232 Mbit
6464 Mbit
128128 Mbit
256256 MbitDDR only
512512 MbitDDR only

SPI Flash (F25L)

CodeDensityNotes
0044 MbitLeading zeros
0088 MbitLeading zeros
01616 MbitLeading zeros
03232 MbitLeading zeros
06464 MbitLeading zeros
128128 Mbit

Parallel Flash (F49L)

CodeDensityNotes
16016 MbitScaled encoding (160 = 16Mb)
32032 MbitScaled encoding
64064 MbitScaled encoding

Package Codes

CodePackageDescription
ATSOPThin Small Outline Package
BBGABall Grid Array
TGTSOP-IITSOP Type II
WGWBGAWindow BGA
BGBGABall Grid Array
PASOPSmall Outline Package
PAIGSOPSOP with Industrial Grade
PGSOP-88-pin SOP

Speed Grades

SDRAM/DDR

CodeSpeedAccess Time
5200MHz5ns
6166MHz6ns
7143MHz7ns
2.5400MHz2.5ns (DDR)

Flash

CodeSpeedNotes
7070nsParallel Flash
100100MHzSPI Flash
104104MHzHigh-speed SPI

Product Families

M12L Series - SDRAM

Part NumberDensityConfigurationSpeed
M12L128168A-6TG128 Mbit8M x 16 x 8 banks166MHz
M12L64164A-5TG64 Mbit4M x 16 x 4 banks200MHz
M12L32164A-6TG32 Mbit2M x 16 x 4 banks166MHz

M14D Series - DDR SDRAM

Part NumberDensityConfigurationSpeed
M14D5121632A-2.5BG512 Mbit32M x 16 x 2400MHz
M14D2561616A-2.5BG256 Mbit16M x 16 x 1400MHz
M14D1281616A-2.5BG128 Mbit8M x 16 x 1400MHz

F25L Series - SPI Flash

Part NumberDensityInterfaceSpeed
F25L004A-100PAIG4 MbitSPI100MHz
F25L008A-100PAIG8 MbitSPI100MHz
F25L016A-100PAIG16 MbitSPI100MHz

F49L Series - Parallel Flash

Part NumberDensityInterfaceSpeed
F49L160UA-70TG16 MbitParallel70ns
F49L320UA-70TG32 MbitParallel70ns

Configuration Encoding (SDRAM/DDR)

The configuration digits after the density encode:

M12L128168A
       |||
       ||+-- Banks (4 or 8)
       |+-- Data bus width (16-bit = 16)
       +-- First digit varies
Config CodeMeaning
16816-bit bus, 8 banks
16416-bit bus, 4 banks
161616-bit bus, 16Mbit config

Handler Implementation Notes

Pattern Matching

// SDRAM - M12L series
"^M12L\\d+.*"

// DDR SDRAM - M14D series
"^M14D\\d+.*"

// SPI Flash - F25L series (also MEMORY_FLASH type)
"^F25L\\d+.*"

// Parallel Flash - F49L series (also MEMORY_FLASH type)
"^F49L\\d+.*"

Package Code Extraction

// Handle hyphenated MPNs - get part after last hyphen
int lastHyphen = upperMpn.lastIndexOf('-');
if (lastHyphen > 0) {
    String suffix = upperMpn.substring(lastHyphen + 1);
    // Strip leading speed grade digits/dots
    String pkgCode = suffix.replaceAll("^[0-9.]+", "");
    // Check PACKAGE_CODES map
}

Density Extraction Complexities

// SPI Flash uses leading zeros: 004, 008, 016
// Parallel Flash uses scaled encoding: 160=16Mbit

// F25L004A -> "4" (strip leading zeros)
// F49L160UA -> "16" (scale down by 10)

Cross-References

SDRAM Equivalents

ESMTSamsungMicronISSI
M12L128168AK4S641632NMT48LC8M16IS42S16800
M12L64164AK4S281632IMT48LC4M16IS42S16400

SPI Flash Equivalents

ESMTWinbondMacronixSST
F25L016AW25Q16MX25L1606ESST25VF016B
F25L008AW25Q80MX25L8006ESST25VF080B

Related Files

  • Handler:
    manufacturers/ESMTHandler.java
  • Component types:
    MEMORY
    ,
    MEMORY_FLASH
    ,
    IC

Learnings & Edge Cases

  • Leading zeros in F25L: SPI Flash density codes have leading zeros (004, 008, 016)
  • Scaled encoding in F49L: Parallel Flash uses 160=16Mbit, 320=32Mbit encoding
  • Configuration encoding: SDRAM part numbers encode bus width and bank count
  • Speed grade in suffix: Speed appears before package code after hyphen (e.g., -6TG = 6ns + TSOP-II)
  • Industrial grade suffix: PAIG = SOP package with Industrial Grade indicator
  • Version letters: A, B, C indicate silicon revisions, not always form/fit/function compatible
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